1. Technical Field
The present invention relates, generally, to etching methods and apparatus for deep sub-micron semiconductor fabrication and, more particularly, to methods and apparatus for plasma etching both metal and inorganic layers in a single chamber.
2. Background Art and Technical Problems
Recent advances in semiconductor processing technology have led to the development of integrated circuit devices employing sub-micron and even deep sub-half-micron feature sizes. Deep sub-micron technologies, involving critical dimensions or feature sizes of less than 0.35 microns, require photo lithographic processes which employ progressively smaller incident wavelengths during the exposure process.
In addition, deep sub-micron feature sizes have spawned the development of sophisticated new photoresist recipes for use with these smaller wavelengths.
Deep sub-micron line widths also tend to drive a reduction in the thickness of the photoresist layers in order to maintain acceptable aspect ratios for the photoresist patterns. However, the use of thinner photoresist pattern layers has resulted in undesired erosion of the patterned microelectronic structure during the metal etch process.
Presently known attempts to preserve the integrity of the microelectronic structures in the presence of thin photoresist layers typically involve the use of metallic barrier layers, such as titanium nitride (TIN), in the metal stack. In addition, organic anti-reflection coating (ARC) layers have been employed on top of metallic barrier layers to help preserve the structural integrity of the photoresist pattern structures. Prior art practice has also utilized an oxide layer prior to the organic ARC layer to function as a hard mask. However, many of the different layers utilized in the prior art require different etching chemistries and etching tools thereby increasing processing time as well as equipment needed for fabricating semiconductor devices.
Although the use of these organic or metallic ARC layers has improved the integrity of the photoresist pattern structures, as well as the integrity of the resulting microelectronic structures, erosion of the patterned microelectronic structure may still occur in the case where all of the photoresist layer erodes away during metal etching, particularly when an organic ARC layer is used in the metal stack without an oxide hard mask.
Alternatively, as contemplated by part of the present invention, an inorganic ARC layer may be used in the metal stack which provides a single optimized film that functions both as an antireflective coating, for preserving the structural integrity of the photoresist pattern structures, and as a hard mask. Unlike the organic ARC layers and metal layers, inorganic ARC layers are typically etched with fluorine based chemistries. Since the process for etching the photoresist and the ARC layer, and the process for etching the metal layer, typically employ different etching tools which are specifically designed to optimize their respective etching processes and etching solution chemistries, the number of process steps and cycle time are increased.
Accordingly, there is a need for composite structures and manufacturing processes that accommodate smaller exposure wavelengths and thinner photoresist layers without jeopardizing the integrity of the microelectronic structures. In addition, there is also a need for composite structures and manufacturing processes which function to decrease the cost and complexity of the semiconductor fabrication process while increasing its efficiency.